1. Field of the Invention
The present invention relates to a plasma display apparatus and a driving method thereof, and more particularly, to a plasma display apparatus for preventing erroneous discharge, and a driving method thereof.
2. Description of the Background Art
In general, a plasma display panel (Hereinafter, referred to as “PDP”) displays an image including a character or a graphic by exciting a phosphor using ultraviolet ray of 147 nm, which is generated when an inert mixture gas such as He+Xe, Ne+Xe, or He+Ne+Xe is discharged. The PDP not only facilitates its thinning and large sizing, but also provides a picture quality greatly improved due to recent technology development. Particularly, a three-electrode alternating current surface discharge type PDP has an advantage of a low voltage driving and a long lifetime because it stores wall charges on a surface in discharge and protects electrodes from sputtering caused by the discharge.
FIG. 1 is a perspective view illustrating a structure of a discharge cell of the conventional three-electrode alternating current surface discharge type plasma display panel.
Referring to FIG. 1, in the conventional three-electrode alternating current surface discharge type PDP, the discharge cell includes a scan electrode (Y) and a sustain electrode (Z) formed on an upper substrate 10, and an address electrode (X) formed on a lower substrate 18. The scan electrode (Y) and the sustain electrode (Z) respectively include transparent electrodes (12Y, 12Z), and metal bus electrodes (13Y and 13Z). The metal bus electrodes (13Y, 13Z) have smaller line widths than the transparent electrodes (12Y, 12Z), and are formed at one-side edges of the transparent electrodes (12Y, 12Z).
The transparent electrodes (12Y and 12Z) are generally formed of indium-tin-oxide (ITO) on the upper substrate 10. The metal bus electrodes (13Y, 13Z) are generally formed of metal such as chrome (Cr) on the transparent electrodes (12Y, 12Z) to reduce a voltage drop caused by the transparent electrodes (12Y, 12Z) having a high resistance. An upper dielectric layer 14 and a protective film 16 are layered on the upper substrate 10 on which the scan electrode (Y) and the sustain electrode (Z) are formed to be in parallel with each other. The wall charges generated in plasma discharge are stored in the upper dielectric layer 14. The protective film 16 prevents the upper dielectric layer 14 from being damaged due to sputtering caused by the plasma discharge, and increases an emission efficiency of secondary electrons. The protective film 16 is generally formed of magnesium oxide (MgO).
A lower dielectric layer 22 and a barrier rib 24 are formed on the lower substrate 18 on which the address electrode (X) is formed. A phosphor layer 26 is coated on the lower dielectric layer 22 and the barrier rib 24. The address electrode (X) is formed to intersect with the scan electrode (Y) and the sustain electrode (Z). The barrier rib 24 is formed to be in parallel with the address electrode (X). The barrier rib 24 prevents ultraviolet ray and visible ray generated due to the plasma discharge, from leaking to an adjacent discharge cell. The phosphor layer 26 is excited using the ultraviolet ray generated in the plasma discharge, thereby generating red, green or blue visible ray. A mixture of inert gases is injected into a discharge space provided between the upper/lower substrates 10 and 18 and the barrier rib 24.
In order to display a grayscale image, the PDP is time-division driven by dividing one frame into several subfields having a different number of emission times. Each subfield is divided into a reset period for initializing a whole screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for embodying grayscale according to the number of discharge times.
The reset period is divided into a setup period for supplying a ramp-up waveform, and a setdown period for supplying a ramp-down waveform. In case where the image is displayed in 256 grayscales, a frame period (16.67 ms) corresponding to a 1/60 second is divided into eight sub-fields as shown in FIG. 2. As described above, each of the eight sub-fields is divided into the reset period, the address period, and the sustain period. The reset period and the address period are the same at each sub-field, whereas the sustain period is increased in a ratio of 2n(n=0, 1, 2, 3, 4, 5, 6, 7) at each sub-field.
FIG. 3 illustrates driving waveforms supplied to two subfields in the PDP.
Referring to FIG. 3, the PDP is driven by dividing each subfield into the reset period, the address period for selecting the cell, and the sustain period for sustaining a discharge of the selected cell.
In a setup period of the reset period, the ramp-up waveform (Ramp-up) is concurrently applied to all scan electrodes CY). The ramp-up waveform (Ramp-up) generates a weak discharge (setup discharge) within the cells of the whole screen, thereby generating the wall charge within the cells. In a setdown period, after the ramp-up waveform is supplied, the ramp-down waveform (Ramp-down) falling from a lower positive voltage than a peak voltage of the ramp-up waveform (Ramp-up) is concurrently applied to the scan electrodes (Y). The ramp-down waveform (Ramp-down) generates a weak erasure discharge within the cells, thereby erasing an unnecessary one of a space charge and the wall charge generated due to the setup discharge, and allowing the wall charge necessary for an address discharge to uniformly remain within the cells of the whole screen.
In the address period, a negative scan pulse (scan) is sequentially applied to the scan electrodes (Y) and at the same time, a positive data pulse (data) is applied to the address electrodes (X). A voltage difference between the scan pulse (scan) and the data pulse (data) is added to the wall charge generated in the reset period, while the address discharge is generated within the cell to which the data pulse (data) is applied. The wall charge is generated within the cells selected by the address discharge.
During the setdown period and the address period, a positive direct current voltage of the sustain voltage (Vs) is supplied to the sustain electrode (Z).
In the sustain period, the sustain pulse (Sus) is alternately supplied to the scan electrodes (Y) and the sustain electrode (Z). If so, in the cell selected by the address discharge, the wall voltage and the sustain pulse (Sus) are added, while the sustain discharge is generated in a surface discharge type between the scan electrode CY) and the sustain electrode (Z) whenever the sustain pulse (Sus) is applied. Upon completion of the sustain discharge, an erasure ramp waveform (erase) having a smaller pulse width is supplied to the sustain electrode (Z), thereby erasing the wall charge from the cell.
In the PDP, the sustain discharge requires a high voltage of hundreds of volts. Accordingly, in order to minimize a driving power necessary for the sustain discharge, an energy recovery device is being used. The energy recovery device recovers a voltage between the scan electrode (Y) and the sustain electrode (Z), and reuses the recovered voltage as a driving voltage in a next discharge.
FIG. 4 illustrates the energy recovery device installed at the scan electrode (Y) to recover a sustain discharge voltage. Actually, the energy recovery device is symmetrically installed even at the sustain electrode (Z) centering on a panel capacitor (Cp).
Referring to FIG. 4, the inventive energy recovery device includes an inductor (L) connected between the panel capacitor (Cp) and a source capacitor (Cs); first and third switches (S1, S3) connected to be in parallel with each other between the source capacitor (Cs) and the inductor (L); second and fourth switches (S2, S4) connected to be in parallel with each other between the panel capacitor (Cp) and the inductor (L); and diodes (D5, D6) each installed between the first and third switches (S1, S3) and the inductor (L).
The panel capacitor (Cp) equivalently represents an electrostatic capacitance formed between the scan electrode (Y) and the sustain electrode (Z). The second switch (S2) is connected to the sustain voltage source (Vs), and the fourth switch (S4) is connected to a ground voltage source (GND). The source capacitor (Cs) recovers the voltage charged to the panel capacitor (Cp) in the sustain discharge, and is charged with the recovered voltage, and again supplies the charged voltage to the panel capacitor (Cp).
For this, the source capacitor (Cs) has a capacitance for charging with a voltage of Vs/2 corresponding to a half of the sustain voltage source (Vs). The inductor (L) forms a resonance circuit together with the panel capacitor (Cp). The first to fourth switches (S1 to S4) control a current flow. Fifth and sixth diodes (D5, D6) prevent a reverse flow of current. Internal diodes (D1 to D4) are respectively installed even at the first to fourth switches (S1 to S4) to prevent the reverse flow of current.
FIG. 5 shows a timing diagram illustrating on/off timings of the switches, and a waveform diagram illustrating a waveform of the panel capacitor shown in FIG. 4.
An operation process will be in detail described on the basis of the assumption that before a period of T1, a voltage of 0[V] is charged to the panel capacitor (Cp) and the voltage of Vs/2 is charged to the source capacitor (Cs).
In the period of T1, the first switch (S1) is turned on, thereby forming a current path from the source capacitor (Cs) to the first switch (S1), the inductor (L), and the panel capacitor (Cp). If the current path is formed, the voltage of Vs/2 charged to the source capacitor (Cs) is supplied to the panel capacitor (Cp). At this time, the sustain voltage (Vs), which is two times as much as a voltage of the source capacitor (Cs), is charged to the panel capacitor (Cp) owing to a series resonance circuit constituted of the inductor (L) and the panel capacitor (Cp). Actually, a little lower voltage than the sustain voltage (Vs) is charged to the panel capacitor (Cp).
In a period of T2, the second switch (S2) is turned on. If so, a voltage of the sustain voltage source (Vs) is supplied to the panel capacitor (Cp). If so, the voltage of the panel capacitor (Cp) is prevented from falling below a reference voltage (Vs). Accordingly, the sustain discharge is stably generated. The voltage of the panel capacitor (Cp) rises approximately up to the sustain voltage (Vs) during the period of T1. Therefore, an external supply voltage can be minimized during the period of T2. That is, power consumption can be reduced.
In a period of T3, the first switch (S1) is turned off. At this time, the panel capacitor (Cp) sustains the sustain voltage (Vs).
In a period of T4, a second switch (S2) is turned off and a third switch (S3) is turned on. If the third switch (S3) is turned on, a current path from the panel capacitor (Cp) to the inductor (L), the third switch (S3), and the source capacitor (Cs) is formed, thereby recovering the charged voltage of the panel capacitor (Cp) to the source capacitor (Cs). At this time, the voltage of Vs/2 is charged to the source capacitor (Cs).
In a period of T5, a third switch (S3) is turned off and a fourth switch (S4) is turned on. If the fourth switch (S4) is turned on, a current path between the panel capacitor (Cp) and the ground voltage source (GND) is formed, thereby allowing the voltage of the panel capacitor (Cp) to fall down to 0[V]. In a period of T6, a state of the period of T5 is sustained for a predetermined time. Actually, an alternating current driving pulse supplied to the scan electrode (Y) and the sustain electrode (Z) is obtained by periodically repeating the periods of T1 to T6.
However, if the PDP is driven at a high temperature (above 40° C.) or a low temperature (below 0° C.) or has a high resolution, erroneous discharge is generated. In a detailed description, as shown in FIGS. 6A and 6B, the PDP generally supplies a scan pulse in a sequence, to select the discharge cell to be turned on. Accordingly, even in the discharge cells respectively formed along the scan electrodes (Y), the address discharge is sequentially generated corresponding to a supply sequence of the scan pulse.
If the address discharge is sequentially generated, an unstable address discharge is generated in the discharge cells having a later scan sequence, that is, in the discharge cells for supplying the scan pulse in a latter half of the address period. In other words, in the discharge cells where the wall charges formed in the reset period are recombined and the scan pulse is supplied in the latter half of the address period, the unstable address discharge (sufficient wall charge is not formed) is generated. Due to the unstable address discharge, the wall charge is not sufficiently formed and the sustain discharge is not generated in the sustain period. This phenomenon is much caused when the PDP is driven at the high temperature or at the low temperature or the panel has a larger resolution.
In the experiment of a specific PDP, the unstable sustain discharge is generated in the discharge cells having an earlier scan sequence. This phenomenon is expected to be caused due to the recombination of the wall charges, which are formed by the address discharge in the discharge cells having the earlier scan sequence. This phenomenon is much caused when the PDP is driven at the high temperature or at the low temperature or the panel has the larger resolution.